The present disclosure relates in general to semiconductor devices and their manufacture. More specifically, the present disclosure relates to the fabrication of vertically stacked nanowire transistors having improved source to drain sheet resistance.
Transistors are semiconductor devices commonly found in a wide variety of integrated circuits. A transistor is essentially a switch. When a voltage is applied to a gate of the transistor that is greater than a threshold voltage, the switch is turned on, and current flows through the transistor. When the voltage at the gate is less than the threshold voltage, the switch is off, and current does not flow through the transistor.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. Complementary metal oxide semiconductor (CMOS) is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions.
Gate-all-around (GAA) nanowire channel field-effect transistors (FETs) enable feature scaling beyond current planar CMOS technology. In its basic form, a nanowire-based FET includes a source region, a drain region and stacked nanowire channels between the source and drain regions. A gate which surrounds the stacked nanowire channels regulates electron flow through the nanowire channels between the source and drain regions. Forming GAA nanowires from alternating epitaxial layers of nanowire silicon (Si) and sacrificial silicon germanium (SiGe) provides superior channel electrostatics control, which is necessary for continuously scaling gate lengths down to seven (7) nanometer technology and below. However, the inclusion of stacked, strained Si/SiGe nanowire/sacrificial layers in the channel region of a GAA nanowire FET structure makes junction design and extension series resistance (Rext) reduction difficult. A reduction in Rext would lead to enhanced driver current performance.